About Me
I am currently working at Meta as a Research Scientist. Here, I work alongside a team of brilliant engineers to build and maintain a multi-tenant compute-farm for processing video transformations efficiently in a massive distributed system.
Before that, I earned my Ph.D. in Computer Science at the University of California, Riverside under the joint supervision of Professor Nael Abu-Ghazaleh and Professor Rajiv Gupta. My research endeavours focused on Computer Architecture and Hardware Accelerators for irregular applications. My goal was to enable the software engineers to fully harness the potential of massively parallel applications using specialized accelerators and architectural extensions. My work involved (i) developing hardware-optimized decoupled computation models for graph processing and machine learning algorithms; and (ii) developing large-scale multicore accelerators to extract the parallelism in these applications.
Download my resumé.
- Computer Architecture
- Hardware Accelerators
- Reconfigurable Computing
- Parallel & Distributed Systems
- Heterogeneous Architecture
- Machine Learning & Artificial Intelligence
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PhD in Computer Science, 2016-2021
University of California, Riverside
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MS in Computer Science
University of California, Riverside
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BS in Electrical Engineering, 2014
Bangladesh University of Engineering & Technology
Latest
Our collaboration on designing a novel execution model for processing evolving graphs is accepted for publication in ASPLOS 2023.
Kudos to Mahabod and Chao for some brilliant work on taking this idea to completion.
I am beginning my professional career at Meta in the role of Research Scientist on October 11, 2021.
I have defended my PhD thesis on September 30, 2021. End of a grand journey.
Our paper on streaming graph analytics accelerator is appearing on MICRO-2021 to take place on October 18-21, 2021.
Completed summer internship as Software Engineer at Micron Technology
- Worked in the development of a simulator for a near-memory computing accelerator.
Two of our papers have been accepted at MICRO-2020 to take place on October 19-21, 2020
- GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing
- BOW: Breathing Operand Windows to Exploit Bypassing in GPUs
Experience
Research
Graph Neural Network Accelerator
- Characterizing GNN behavior to identify parallelization opportunities.
- Exploring hardware constructs to eliminate memory bottlenecks in large graphs.
Event-Driven Graph Processing Framework
- Developing an event-driven processing model for graph processing algorithms.
- Designing a hardware accelerator architecture for scalable and optimized event-driven graph processing on FPGA and ASIC.
- Developing an MPI-driven cycle-accurate hardware simulator on top of Structural Simulation Toolkit (SST) for fast prototyping and scalability analysis on large graphs.
Parallel Discrete Events Simulation Accelerator
- Designing a generalized and modular architectural framework for fast development of Parallel Discrete Events Simulators on reconfigurable platforms.
- Implemeting the framework using Verilog and Chisel on a Convey Wolverine Coprocessor.
One-shot Gesture Recognition
- Developing novel algorithms for detection of individual gestures from video containing depth data.
- Extracting and characterizing distinguishing features from motion-history-image of a gesture.
- Developing algorithms for real-time gesture recognition using one-shot learning techniques.
Publications
Contact
- <lastname>@shafiur.me
- Menlo Park, CA 94025