Avatar

Shafiur Rahman

PhD candidate in Computer Science

University of California, Riverside

About Me

Hello! I am a graduate student in the University of California, Riverside currently working towards earning a PhD degree under the mentorship of Professor Nael Abu-Ghazaleh.

I work on Computer Architecture and Hardware Accelerators. My goal is to enable the software engineers to fully harness the potential of massively parallel applications using specialized acclerators and architectural extensions. My current research focuses on (i) developing hardware-optimized decoupled computation model for graph processing and machine learning algorithms; and (ii) developing large-scale multicore accelerators to extract the parallelism in these applications.

Interests

  • Computer Architecture
  • Hardware Accelerators
  • Reconfigurable Computing
  • Parallel & Distributed Systems
  • Heterogeneous Architecture
  • Machine Learning & Artificial Intelligence

Education

  • PhD candidate in Computer Science, 2016-Present

    University of California, Riverside

  • MS in Computer Science

    University of California, Riverside

  • BS in Electrical Engineering, 2014

    Bangladesh University of Engineering & Technology

Latest

Completed summer internship at Western Digital, Platforms and Systems Concept Group

Two of our papers have been accepted at MICRO-2020 to take place on October 19-21, 2020

  • GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing
  • BOW: Breathing Operand Windows to Exploit Bypassing in GPUs

Research

Graph Neural Network Accelerator

  • Characterizing GNN behavior to identify parallelization opportunities.
  • Exploring hardware constructs to eliminate memory bottlenecks in large graphs.

Event-Driven Graph Processing Framework

  • Developing an event-driven processing model for graph processing algorithms.
  • Designing a hardware accelerator architecture for scalable and optimized event-driven graph processing on FPGA and ASIC.
  • Developing an MPI-driven cycle-accurate hardware simulator on top of Structural Simulation Toolkit (SST) for fast prototyping and scalability analysis on large graphs.

Parallel Discrete Events Simulation Accelerator

  • Designing a generalized and modular architectural framework for fast development of Parallel Discrete Events Simulators on reconfigurable platforms.
  • Implemeting the framework using Verilog and Chisel on a Convey Wolverine Coprocessor.

One-shot Gesture Recognition

  • Developing novel algorithms for detection of individual gestures from video containing depth data.
  • Extracting and characterizing distinguishing features from motion-history-image of a gesture.
  • Developing algorithms for real-time gesture recognition using one-shot learning techniques.

Publications

(2020). BOW: Breathing Operand Windows to Exploit Bypassing in GPUs. Proceedings of the 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO’20).

PDF

(2020). GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing. Proceedings of the 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO’20).

PDF

(2019). PDES-A: Accelerators for Parallel Discrete Event Simulation Implemented on FPGAs. ACM Transactions on Modeling and Computer Simulation (TOMACS).

PDF DOI

(2017). PDES-A: A Parallel Discrete Event Simulation Accelerator for FPGAs. Proceedings of the 2017 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation.

PDF DOI

(2014). A novel adaptive volterra filter to compensate for speaker non-linearity. 8th International Conference on Electrical and Computer Engineering.

PDF DOI

(2013). A template matching approach of one-shot-learning gesture recognition. Pattern Recognition Letters.

PDF DOI

(2013). Temporal segmentation of gestures using gradient orientation of depth images. 2013 International Conference on Informatics, Electronics and Vision (ICIEV).

PDF DOI

(2013). One-Shot-Learning Gesture Recognition Using Motion History Based Gesture Silhouettes. The 1st International Conference on Industrial Application Engineering 2013 (ICIAE2013).

PDF

(2012). Gesture recognition with depth images — A simple approach. 2012 Proceedings of SICE Annual Conference (SICE).

PDF

Experience

 
 
 
 
 

RAMP Next-Generation Platforms Technology Intern

Western Digital

Jun 2020 – Aug 2020 Milpitas, CA
 
 
 
 
 

Graduate Research Assistant

University of California, Riverside

Aug 2016 – Present
 
 
 
 
 

Software Engineer

Therap Services Ltd

Jul 2014 – Nov 2015 Dhaka, Bangladesh

Contact