Shafiur Rahman

Shafiur Rahman

Research Scientist


About Me

I am currently working at Meta as a Research Scientist. Here, I work alongside a team of brilliant engineers to build and maintain a multi-tenant compute-farm for processing video transformations efficiently in a massive distributed system.

Before that, I earned my Ph.D. in Computer Science at the University of California, Riverside under the joint supervision of Professor Nael Abu-Ghazaleh and Professor Rajiv Gupta. My research endeavours focused on Computer Architecture and Hardware Accelerators for irregular applications. My goal was to enable the software engineers to fully harness the potential of massively parallel applications using specialized accelerators and architectural extensions. My work involved (i) developing hardware-optimized decoupled computation models for graph processing and machine learning algorithms; and (ii) developing large-scale multicore accelerators to extract the parallelism in these applications.

Download my resumé.

  • Computer Architecture
  • Hardware Accelerators
  • Reconfigurable Computing
  • Parallel & Distributed Systems
  • Heterogeneous Architecture
  • Machine Learning & Artificial Intelligence
  • PhD in Computer Science, 2016-2021

    University of California, Riverside

  • MS in Computer Science

    University of California, Riverside

  • BS in Electrical Engineering, 2014

    Bangladesh University of Engineering & Technology



C, C++, Python, CUDA

Hardware Design

Verilog, Xilinx Vivado, ModelSim, EDA Toolchains


Cycle-accurate simulation - Gem5, SST


Our collaboration on designing a novel execution model for processing evolving graphs is accepted for publication in ASPLOS 2023.

Kudos to Mahabod and Chao for some brilliant work on taking this idea to completion.

I am beginning my professional career at Meta in the role of Research Scientist on October 11, 2021.

I have defended my PhD thesis on September 30, 2021. End of a grand journey.

Our paper on streaming graph analytics accelerator is appearing on MICRO-2021 to take place on October 18-21, 2021.

Completed summer internship as Software Engineer at Micron Technology

  • Worked in the development of a simulator for a near-memory computing accelerator.

Two of our papers have been accepted at MICRO-2020 to take place on October 19-21, 2020

  • GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing
  • BOW: Breathing Operand Windows to Exploit Bypassing in GPUs


Research Scientist
Oct 2021 – Present Menlo Park, CA
Micron Technology
Software Engineering Intern
Apr 2021 – Sep 2021 Allen, TX
Western Digital
RAMP Next-Generation Platforms Technology Intern
Jun 2020 – Aug 2020 Milpitas, CA
University of California, Riverside
Graduate Research Assistant
Aug 2016 – Sep 2021
Therap Services Ltd
Software Engineer
Jul 2014 – Nov 2015 Dhaka, Bangladesh


Graph Neural Network Accelerator


  • Characterizing GNN behavior to identify parallelization opportunities.
  • Exploring hardware constructs to eliminate memory bottlenecks in large graphs.

Event-Driven Graph Processing Framework


  • Developing an event-driven processing model for graph processing algorithms.
  • Designing a hardware accelerator architecture for scalable and optimized event-driven graph processing on FPGA and ASIC.
  • Developing an MPI-driven cycle-accurate hardware simulator on top of Structural Simulation Toolkit (SST) for fast prototyping and scalability analysis on large graphs.

Parallel Discrete Events Simulation Accelerator


  • Designing a generalized and modular architectural framework for fast development of Parallel Discrete Events Simulators on reconfigurable platforms.
  • Implemeting the framework using Verilog and Chisel on a Convey Wolverine Coprocessor.

One-shot Gesture Recognition


  • Developing novel algorithms for detection of individual gestures from video containing depth data.
  • Extracting and characterizing distinguishing features from motion-history-image of a gesture.
  • Developing algorithms for real-time gesture recognition using one-shot learning techniques.


(2023). CommonGraph: Graph Analytics on Evolving Data. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’23).


(2021). JetStream: Graph Analytics on Streaming Data with Event-Driven Hardware Accelerator. Proceedings of the 54th IEEE/ACM International Symposium on Microarchitecture (MICRO'21).

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(2020). GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing. Proceedings of the 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO'20).

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(2020). BOW: Breathing Operand Windows to Exploit Bypassing in GPUs. Proceedings of the 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO'20).


(2019). PDES-A: Accelerators for Parallel Discrete Event Simulation Implemented on FPGAs. ACM Transactions on Modeling and Computer Simulation (TOMACS).


(2017). PDES-A: A Parallel Discrete Event Simulation Accelerator for FPGAs. Proceedings of the 2017 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation.


(2014). A novel adaptive volterra filter to compensate for speaker non-linearity. 8th International Conference on Electrical and Computer Engineering.


(2013). A template matching approach of one-shot-learning gesture recognition. Pattern Recognition Letters.


(2013). Temporal segmentation of gestures using gradient orientation of depth images. 2013 International Conference on Informatics, Electronics and Vision (ICIEV).


(2013). One-Shot-Learning Gesture Recognition Using Motion History Based Gesture Silhouettes. The 1st International Conference on Industrial Application Engineering 2013 (ICIAE2013).

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(2012). Gesture recognition with depth images — A simple approach. 2012 Proceedings of SICE Annual Conference (SICE).

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  • Menlo Park, CA 94025